The present invention relates to a technology for manufacturing an electronic device such as a semiconductor device, and particularly to a technology which is effective when applied to an electronic device (semiconductor device) in which, over the main surface of a base member having an electronic component such as a semiconductor chip mounted thereon, another wiring substrate is further stacked.
In recent years, demand for the miniaturization of an electronic device such as a semiconductor device has increasingly grown stronger. Accordingly, it is assumed that forming each of a plurality of electronic components from one semiconductor device is effective in reducing a mounting region for a semiconductor device, chip components, and the like to be mounted over a mounting substrate (motherboard).
Examples of a structure of such a semiconductor device include one as shown in Japanese Unexamined Patent Publication No. 2008-288490 (Patent Document 1 (FIG. 2D)) in which a second substrate is stacked over a first substrate having chip components mounted thereon, and electronic components are mounted over the second substrate.